History of Q35_X38-SINIT
========================

v18:
    -  Discontinued support for the Intel(R) X38 Express chipset
    -  Fix a bug in the order that components of PCR 17 were hashed in so that
       it now matches the order in the MLE Developers Guide.
    -  Support for LCP version 1.
    -  Enforces that LCP Data blobs must reside in DMA-protected memory.
    -  Fixed bug in MLE page table handling so that now page tables can have
       multiple PGDPTR and PDE entries.
    -  Returns MLE page table base addr in ECX after SENTER.
    -  Fixed a misconfiguration regarding handling of 64bit registers, as
       reported in security advisory SA-0002.
    -  Miscellaneous bug fixes.

v17:
    -  Fixed a bug that caused a reset on successive launches
       (i.e. SENTER ... SEXIT ... SENTER ...) when PMRs were left enabled
       between launches.
    -  Small changes to errorcodes list.
    -  Misc. fixes.

v16:
    -  When using protected memory regions, the Measured Launch Environment
       (MLE) should be placed within this region completely to ensure
       protections from DMA attacks on the MLE. In order to ensure the MLE is
       placed within this region the TXT SINIT Authenticated Code Module has
       been enhanced to check if the VT-d PMRs are enabled and if so that the
       region(s) they specify are the same as that specified in the MLE
       OsSinitData structure. SINIT should fail if they do not match exactly,
       hence, providing DMA protections for that region.
    -  Updated to latest version of data structures and behaviors as specified
       in the May 2008 Intel(R) TXT MLE Developer's Manual
