/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
 * Copyright (c) 2023 Amlogic, Inc.
 * Author: Hongyu Chen <hongyu.chen1@amlogic.com>
 */
#ifndef _DT_BINDINGS_AMLOGIC_T7_POWER_H
#define _DT_BINDINGS_AMLOGIC_T7_POWER_H

#define PWRC_T7_DSPA_ID			0
#define PWRC_T7_DSPB_ID			1
#define PWRC_T7_DOS_HCODEC_ID		2
#define PWRC_T7_DOS_HEVC_ID		3
#define PWRC_T7_DOS_VDEC_ID		4
#define PWRC_T7_DOS_WAVE_ID		5
#define PWRC_T7_VPU_HDMI_ID		6
#define PWRC_T7_USB_COMB_ID		7
#define PWRC_T7_PCIE_ID			8
#define PWRC_T7_GE2D_ID			9
#define PWRC_T7_SRAMA_ID		10
#define PWRC_T7_SRAMB_ID		11
#define PWRC_T7_HDMIRX_ID		12
#define PWRC_T7_VI_CLK1_ID		13
#define PWRC_T7_VI_CLK2_ID		14
#define PWRC_T7_ETH_ID			15
#define PWRC_T7_ISP_ID			16
#define PWRC_T7_MIPI_ISP_ID		17
#define PWRC_T7_GDC_ID			18
#define PWRC_T7_CVE_ID			18
#define PWRC_T7_DEWARP_ID		19
#define PWRC_T7_SDIO_A_ID		20
#define PWRC_T7_SDIO_B_ID		21
#define PWRC_T7_EMMC_ID			22
#define PWRC_T7_MALI_SC0_ID		23
#define PWRC_T7_MALI_SC1_ID		24
#define PWRC_T7_MALI_SC2_ID		25
#define PWRC_T7_MALI_SC3_ID		26
#define PWRC_T7_MALI_TOP_ID		27
#define PWRC_T7_NNA_CORE0_ID		28
#define PWRC_T7_NNA_CORE1_ID		29
#define PWRC_T7_NNA_CORE2_ID		30
#define PWRC_T7_NNA_CORE3_ID		31
#define PWRC_T7_NNA_TOP_ID		32
#define PWRC_T7_DDR0_ID			33
#define PWRC_T7_DDR1_ID			34
#define PWRC_T7_DMC0_ID			35
#define PWRC_T7_DMC1_ID			36
#define PWRC_T7_NOC_ID			37
#define PWRC_T7_NIC2_ID			38
#define PWRC_T7_NIC3_ID			39
#define PWRC_T7_CCI_ID			40
#define PWRC_T7_MIPI_DSI0_ID		41
#define PWRC_T7_SPICC0_ID		42
#define PWRC_T7_SPICC1_ID		43
#define PWRC_T7_SPICC2_ID		44
#define PWRC_T7_SPICC3_ID		45
#define PWRC_T7_SPICC4_ID		46
#define PWRC_T7_SPICC5_ID		47
#define PWRC_T7_EDP0_ID			48
#define PWRC_T7_EDP1_ID			49
#define PWRC_T7_MIPI_DSI1_ID		50
#define PWRC_T7_AUDIO_ID		51

#endif
